Comments on: Hyperthreaded Memory http://www.airs.com/blog/archives/92 Ian Lance Taylor Wed, 7 Jan 2009 02:43:13 +0000 http://wordpress.org/?v=1.5.2 Comment on Hyperthreaded Memory by: Ian Lance Taylor http://www.airs.com/blog/archives/92#comment-6884 Fri, 16 Nov 2007 15:18:34 +0000 http://www.airs.com/blog/archives/92#comment-6884 It seems like a very plausible scenario to me. It seems like a very plausible scenario to me.

]]> Comment on Hyperthreaded Memory by: ncm http://www.airs.com/blog/archives/92#comment-6806 Thu, 15 Nov 2007 04:29:23 +0000 http://www.airs.com/blog/archives/92#comment-6806 As the complexity of caches and memory systems grows without bound, my expectation that they will all be implemented correctly approaches zero. Joe Coder's ability to program these memory systems correctly starts out near zero, despite his great confidence in his skills. Bjarne Stroustrup reports that the "lockless programming" literature consists of alternations between "look, you can do this" and "no, that doesn't work". Eliminating shared memory between processors would simplify cache systems to the point of reliability. With MPI and pipes, it seems possible to code them reliably as well. MPI and kernels, then, would need to be right, but that means only a few people need know what they're doing (unlike Joe Coder); if they get it wrong, they can fix it (unlike cache subsystems). As the complexity of caches and memory systems grows without bound, my expectation that they will all be implemented correctly approaches zero. Joe Coder’s ability to program these memory systems correctly starts out near zero, despite his great confidence in his skills. Bjarne Stroustrup reports that the “lockless programming” literature consists of alternations between “look, you can do this” and “no, that doesn’t work”.

Eliminating shared memory between processors would simplify cache systems to the point of reliability. With MPI and pipes, it seems possible to code them reliably as well. MPI and kernels, then, would need to be right, but that means only a few people need know what they’re doing (unlike Joe Coder); if they get it wrong, they can fix it (unlike cache subsystems).

]]> Comment on Hyperthreaded Memory by: Ian Lance Taylor http://www.airs.com/blog/archives/92#comment-6802 Thu, 15 Nov 2007 02:02:46 +0000 http://www.airs.com/blog/archives/92#comment-6802 Thanks for the note. Yes, it probably is something like a micro-kernel. I recall that Mach had some sort of general I/O portal, but I never looked at how it is implemented. Thanks for the note. Yes, it probably is something like a micro-kernel. I recall that Mach had some sort of general I/O portal, but I never looked at how it is implemented.

]]> Comment on Hyperthreaded Memory by: ianw http://www.airs.com/blog/archives/92#comment-6796 Wed, 14 Nov 2007 22:21:11 +0000 http://www.airs.com/blog/archives/92#comment-6796 "In this model, we need high bandwidth communication between the processors which does not to through shared memory. Ideally this will be modeled as a communication queue which can exist entirely in userland. Then different threads can exchange data via these communication queues." This sounds a lot like a microkernel to me ... “In this model, we need high bandwidth communication between the processors which does not to through shared memory. Ideally this will be modeled as a communication queue which can exist entirely in userland. Then different threads can exchange data via these communication queues.”

This sounds a lot like a microkernel to me …

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